1. Field of the Invention
This invention relates to a high density, high performance memory cell. In particular, it relates to a dynamic storage device achieving high packing density that can be fabricated utilizing simple processing steps.
2. Prior Art
Developmental work in semiconductor memories and in particular to binary random access memories (RAM) has resulted in the number of bits of storage per chip increasing to approximately 64,000. At the same time, the cost per bit, due to increased processing efficiencies, has dramatically decreased. The computer industry has a standing requirement for increased storage capacity by the formation of small, reliable memory cells formed on a single chip. The formation of a large number of memory cells on a chip yields economies, in terms of cost per bit, so long as the processing steps allow for acceptable yield rates.
Individual chips interconnect to form a memory array. Since a significant portion of the total cost in the production of semiconductor chips is in the steps of interconnecting, packaging, testing, and the like, an increase in memory cell count per chip decreases a total number of chips which must be handled to form the memory array. Accordingly, a pacing criteria in the definition of improved semiconductor memories is to achieve greater packing densities while at the same time maintaining the process as simple as possible.
Within the prior art, a host of different techniques of forming descrete cells for semiconductor memories are known. Reference is made to U.S. Pat. No. 4,164,751 which summarizes a number of methods of making memory cells used in the construction of semiconductor memory chips.
A second requirement, mitigating against high packing density, is that each cell have a charge capacity per unit area which is at an acceptable level so that the charge stored therein is distinguishable from noise in the memory. As packing density increases, the number of cells per chip increases and therefore the size of each cell for a given chip area decreases. Accordingly, the amount of charge that can be stored in an individual cell decreases, reaching a point where the amount of stored charged is unacceptably low. A balancing packing density vs. signal strength is therefore a serious consideration.
U.S. Pat. No. 3,852,800 describes a memory storage cell utilizing the inherent metal-insulator-semiconductor capacitance and the P-N junction capacitance at the source node of a field effect transistor. In order to enhance charge storage, an extended portion of the source diffusion in combination with overlying thin oxide and metal layers forms a capacitor. Accordingly, the '800 patent utilizes a single IGFET with the binary data represented in the form of a stored charge arranged in a matrix of memory cells to define a random access memory.
U.S. Pat. No. 4,122,543 shows a variation of the MIS structure shown in the '800 patent by utilizing a second storage state having an MIIS element whose electric charge is controlled by the width of the channel formed between two depletion zones in a substrate which forms a first storage state. The MIIS structure is formed by a layer of metal covered by two layers of an insulator, the second being very thin and finally by semiconductor layer. The MIIS structure in the '543 patent acts when a positive voltage is applied to the metal layer with respect to the semiconductor layer. Electrons from the semiconductor pass through the thinnest insulating layer by tunnel effect and are trapped at the interface between the two interface layers. Alternatively, the electrons can be trapped in an ion implant area with the charge therein retained for a long period of time, in the order of one year. Erasure of the charge is obtained by applying a voltage in the opposite direction.
U.S. Pat. No. 4,164,751 also relates to a memory system integrated in a semiconductor substrate having an N+ region on a first surface of a semiconductor substrate forming a bit line and transistor source. A storage region is defined in the same surface spaced from the N+ region and comprises an N- type implant in the substrate near the first surface together with a P type implant in the substrate beneath the N type implant. An insulating layer is formed with a storage gate region and a transfer gate region formed overlying the insulating layer.
In each memory cell, the charge is stored in both an oxide capacitor and in a depletion capacitor. The oxide capacitor is defined by the storage gate and an N type implant separated by an insulating layer. The depletion capacitor is formed by a storage region defined by two ion implants near the surface of the memory cell.
Accordingly, while a variety of prior art devices utilize charge storage techniques, in MIS capacitors, P -N junction capacitance and depletion layer capacitance, all are categorized by a requirement of multiple, difficult processing steps. Hence, there still exists a requirement for a memory cell achieving high packing density yet manufactured by a relatively simple process. Power dissipation also remains a problem particularly in IGFET devices. While high packing densities are achieved, power dissipation in such devices remains a consideration. This shortcoming restricts overall array size tending to restrict overall memory size. Moreover special measures must be taken for power conditioning.
It is an object of this invention to define a dynamic memory cell having current flows smaller than in IGFET devices and one eliminating the requirement for thin film dielectrics.
Another object of this invention is to provide a dynamic memory array having low power dissipation and capable of being manufactured utilizing simple manufacturing techniques.
A further object of this invention is to provide a dynamic memory array achieving high packing density while having low power dissipation.